Technical Field
The present invention relates to electronic field, and in particular, to a LVDS data recovery method and circuit.
Related Art
FIG. 1 shows a traditional low voltage differential signaling (referred to below as LVDS) system, wherein an LVDS transmitter TX launches N channel data, Tx1, . . . , TxN and sends a clock signal TxCk at the same time. These signals arrive at the side of receiver RX via cables, etc. At RX, the corrective phase locked loop PLL takes the TxCK as reference clock, to generate a clock MxCk whose frequency is M times of the TxCK. For video applications of low voltage differential signal, M can be selected to be 3.5 or 7. Due to deviation and channel adaptation problems, the clock MxCk used to sample the data signal may not be precisely aligned to the center of the data signals, therefore, it may lead to data-read error, and the Bit-Error Rate BERT may be much higher than pre-set level.
In order to solve the problems, a traditional method is based on a way of training sequences or training pattern to accurately aim at phase of the MxCk clock. For example, the RX sends a training sequence 101010 to the Tx, and then the Rx receives a data vector D<6:0> from the Tx. A state machine FSM adjusts the phase of MxCk on the basis of comparison results of the training sequences and the received data vector, so as to ensure that the clock edge of MxCk is just located in the center of the data. This method requires Tx sending a training sequence like 101010 . . . or 010101, which is not available in many schemes, thus leading to limited application.
FIG. 2 illustrates another scheme without training sequence, wherein the launched clock signal TxCk is sampled by adopting a correct phase of MxCk. After the phase has been accurately aligned, the pattern 1100011 will be displayed in recovery data D<6:0> shown in FIG. 2. The number of application phases is shown to be eight in FIG. 2, the eight phases can be obtained by a multiple-phase voltage-controlled oscillator in the phase locked loop PLL. In order to obtain higher precision phase, the PLL can be replaced with the DLL as shown in FIG. 3, so as to achieve effect of finer phase step.
The second scheme can work well in the case of low speed, but the clock MxCK or NxCK (being selected depending on a single- or double-edge sampling). used to sample in the case of high speed of TxCk may sample an edge of the clock signal TxCK, which may lead to reading results shown in FIG. 4a, especially lead to the case of the SSC (Spread-Spectrum Clocking) of TxCK shown in FIG. 4b. For the lower case in FIG. 4a, when the recovery data is 1x00x11, it may be any one of 1100011, 1100111, 1000011 and 1000111. If the state machine FSM determines 1 x00x11 to be 1100011, it will stop adjusting the MxCK clock phase, and selects current phase for data sampling. However, as it can be seen from the figure, the sampling clock MxCK is not aimed at the center of the data, thus problems may arise.